In the integrated circuit industry, the bonding and interconnecting of integrated circuit elements to the next level of integration is critical to the success of manufacturing highly dense integrated circuits. Bonding technologies such as tape automounted bonding (TAB), flip chip technology, and chip on glass (COG) have been developed to improve the interconnection and packaging of the integrated circuits. Conventionally, these technologies require that Au bumps be fabricated for the joining of the integrated circuit elements. The material Au provides good interconnections because it is not easily dioxized. The low hardness of Au also makes the interconnections more adaptable to stress and strain.
In semiconductor FABs, processes involving the use of Au have been generally disallowed in that the characteristic of a semiconductor device can be affected by Au. Therefore, the process of forming the Au bumps must be carefully separated and performed in a different manufactory. Both the possibility of contaminating the integrated circuits and the cost of fabrication are greatly increased.
In order to reduce the cost and simplify the process of forming the interconnecting bumps for an integrated circuits, the formation of composite bumps has been studied and disclosed in recent years. U.S. Pat. No. 5,393,697 issued to Shyh-Ming Chang et al. shows a composite structure and methods of forming the composite bump structure. U.S. Pat. No. 5,431,328 also issued to Shyh-Ming Chang et al. discloses a method of forming a bonded structure that includes solder joints and composite bumps. Both patents were assigned to the same assignee of the present invention. Other related prior arts include Japanese Laid Open Application Nos. 62927/91 and 84917/94.
FIG. 1 shows a composite bump structure disclosed in Japanese Laid Open Application No. 62927/91. The composite bump structure in FIG. 1 consists of a metal layer 12 and a polymer layer 11 formed above an input/output pad 10. The input/output pad 10 is formed on a silicon substrate 13 covered by a passivation layer 14. FIG. 2 shows an alternative composite bump of the prior art disclosed in U.S. Pat. No. 5,393,697. The composite bump comprises a first metal layer 23, a polymer layer 24 and a second metal layer 25. The bump is formed above an input/output pad 22 on a silicon substrate 20 that has a passivation layer 21 deposited thereon.
Although the composite bump comprising a polymer layer as shown in FIG. 1 or 2 offers some advantages for bonding and interconnecting the integrated circuit elements, its testability is an important issue that needs to be addressed. In general, integrated circuits are probed and tested before dies are cut from a wafer. The probing and testing are typically done on the interconnecting bumps. Due to the sharpness and hardness of a probing pin, the metal layer of the composite bump may be broken during the test. The testing result can therefore be inaccurate because the polymer layer below is highly insulating. One solution to the problem is increasing the thickness of the metal layer of the composite bump. The increased metal thickness hardens the composite bump. When composite bumps are connected in the next level of integration, they can not be easily adapted to accommodate the variation in the interface spacing. The quality of interconnection may therefore be degraded. That results in poor contact. The complexity and cost of manufacturing the bumps are also increased.
When polyimide (PI) is used for the polymer layer, the polymer layer in the composite bump is fabricated by an etching process. The top of the polymer layer is generally 10 .mu.m narrower than the bottom on each side due to the etching undercut. Consequently, a large area is required for forming the composite bump. The large bump size makes it difficult to form composite bumps with a fine pitch for interconnecting high density integrated circuit elements that have a large number of input/output pads.